1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to a system for measuring the resistance of signal paths through an interconnect structure for linking an IC tester to test points on an IC to be tested.
2. Description of Related Art
It has become increasing popular to test integrated circuits while they are still in the form of die on a wafer. To do so, an IC tester must contact hundreds or thousands of test points on a wafer through an interconnect structure capable of providing a large number of signal paths between a tester's input/output (I/O) ports and test points on a wafer. Since the I/O ports of an IC tester are distributed over a much wider horizontal area than the test points they access, an interconnect structure linking those I/O ports to the test points can be a relatively complicated structure including more than one interconnected signal routing layer and numerous probes, pins and/or contact points that must be precisely aligned and in good contact with one another to provide the necessary signal paths.
Before testing a wafer we would like to confirm that the interconnect structure can provide the necessary signal paths between the test head and the wafer. A connection failure may arise, for example, due to a contact misalignment, broken, missing or contaminated pins, probes or contact pads, open circuit or short circuit faults within interconnect structures or within test heads. In many applications we also would like to verify that the resistance of a signal path between each test head I/O port and a corresponding test point on a wafer is within acceptable limits. Interconnect structure assemblies are usually designed to provide signal paths having particular resistances, and variations from the intended resistance, due for example to corrosion or contamination on contact pads or the tips of probes, can distort test results.
The resistances of signal paths within an interconnect structure are typically tested during the manufacturing process using conventional resistance measurement equipment accessing ends of the signal paths via small probes. However signal paths within an interconnect structure can fail after it leaves the factory when the structure is in use in an integrated circuit tester, and it is difficult and inconvenient to periodically remove an interconnect structure from a tester and manually test the continuity and resistance of its signal paths. Open and short circuit signal path failures can often be detected, or at least suspected, when an interconnect structure is in use because such path failures normally lead to characteristic patterns of IC test failures. However when a signal path has a resistance that is marginally outside an acceptable range, IC test failures may not exhibit a clear pattern. Some die will pass and some die will fail a test. Thus die can be improperly rejected as failing a test when the source of the failure was in fact the interconnect structure, and it may not be readily apparent that the failures are the fault of the interconnect structure, not the rejected die.
Thus what is needed is a convenient method for quickly measuring the resistance of signal routing paths through an interconnect structure without having to remove it from its working environment.